Palladium Tips

* To pre-allocate specific domains for a palladium database to run on in a script, we can use xeset command. The following is an example

debug . -session new2
xeset bpValue {0.5 0.6}
host cemulx120
download
...

* Use Verigen to generate gate-level schematics

We can do this via command line or via xeDebug GUI.
a. Use xeDebug GUI
There is a RTL/Gate tab in xeDebug GUI.

In the above, we added the instance of "." and generated verilog file of default.v. The instance of "." represents the root of the design.

b. Directly use command at command line.
verigen USERLIB TEST_WRP -inst . -out default.v -bus

In the above, USERLIB is the library, TEST_WRP is the top level design cell.

* How to debug ribbon cable connection and PIN assignment for palladium database

For example, we know PIN_WE_CE0_CH0 is supposed to connect to the WE pin of Channel 0 CE0 of a NAND daughter card. We can remove NAND from the daughter card to avoid it to drive the signal. Then we can force PIN_WE_CE0_CH0 to low and measure the voltage of the WE input. Then force PIN_WE_CE0_CH0 to high and measure the voltage of the WE input of the daughter card. If the voltage measured matches with the high/low level of the daughter card input, then the PIN assignment/ribbon cable connection for this signal is correct.

DDR3 Timing

Reference
-----------
1. How to use SDRAM User's Manual (ELPIDA)
2. How to use DDR SDRAM User's Manual(ELPIDA)
3. How to use DDR2 SDRAM User's Manual(ELPIDA)

A Simple UVM Example for Beginners

Ref [1] is a very good UVM guide for beginners. Ref[2] provides source codes for the examples used in Ref [1]. Below are the steps to try the example out.

QuickStart to Run the Example
----------------------------------------
1. Create a simulation directory and let's use $SIMULATION to represent the directory.
2. Download the source codes for the example UVM codes from Ref [2] and extract it under $SIMULATION. This generates a directory of $SIMULATION/uvm-testbench-tutorial-simple-adder-master.
3. Create a directory $SIMULATION/uvm-src.
4. Download the UVM 1.2 or UVM 1.1d source codes from Ref [3] and extract it under uvm-src. This creates a directory of $SIMULATION/uvm-src/uvm-1.2 or $SIMULATION/uvm-src/uvm-1.1d.
5. Switch to the directory of $SIMULATION/uvm-testbench-tutorial-simple-adder-master.
6. If UVM 1.2 source code is used in step 4, we need to edit the UVM_HOME variable in the file of Makefile.vcs.

Change
UVM_HOME = ../uvm-src/uvm-1.1d
to
UVM_HOME = ../uvm-src/uvm-1.2

If uvm-1.1d was downloaded in step 4, we can skip this step.
7. Set up vcs environment so that vcs program can run.
8. Run "make  -f  Makefile.vcs


Add Waveform Dumping Feature
------------------------------------------
Ref [4] and Ref [5] are two good references of how to use vcs to dump waveform. Below are my working steps.

1. Added the following in the test-bench code of simpleadder_tb_top.sv.

`ifdef DUMP_FSDB
initialbegin
  $fsdbDumpfile("test.fsdb");
  $fsdbDumpvars;
end
`endif

2. In Makefile.vcs, added below options for vcs to compile the test-bench to do waveform dumping.

+define+DUMP_FSDB \
-P $(NOVAS_HOME)/share/PLI/VCS/LINUX/novas.tab $(NOVAS_HOME)/share/PLI/VCS/LINUX/pli.a \

NOTE:  The environment variable NOVAS_HOME was set to the path of the verdi install directory in my environment.

3. Run "make -f Makefile.vcs" again. The file test.fsdb is generated during the simulation and I can run "verdi -ssf test.fsdb" to view the waveform generated.

If removing "+define+DUMP_FSDB" option for vcs in step 2, then the code added in step 1 won't take effect and test.fsdb will not be generated.

Both Ref[4],[5] mentioned add $(NOVAS_INST_DIR)/share/PLI/lib/$(PLATFORM) as one of $LD_LIBRARY_PATH searching paths. But the experiment shows this is not needed.

References
-------------
1. https://colorlesscube.com/uvm-guide-for-beginners/
2. https://github.com/naragece/uvm-testbench-tutorial-simple-adder
3. http://accellera.org/downloads/standards/uvm
3. https://verificationacademy.com/cookbook/questa/compilinguvm
4. https://blogs.mentor.com/verificationhorizons/blog/2011/03/08/using-the-uvm-10-release-with-questa/
4. http://chanrui.blogspot.com/2012/03/verdi-and-vcs-cosim.html
5. http://www.cnblogs.com/lunix/archive/2011/03/20/vcs_and_verdi_cosim.html
6. https://github.com/hjking/mydotfiles/blob/master/vim/vim_wiki/eda/verdi/Linking_And_Dumping.wiki

Rule Violation (RTSTAT-6) Partial Conflict issue on Vivado rev 2015.4

For Vivado 2015.4, I hit an error like the following when click "Generate Bitstream" after implementation is done.
ERROR: [DRC 23-20] Rule violation (RTSTAT-6) Partial Conflict - 18640 net(s) have a partial conflict. The problem bus(es) and/or net(s) are .....

The errors occured when I use the implemenation strategy of "Vivado Implementation Defaults". Also tried "Performance_Explore", it does not help. It is found that when I try the implementation strategy of "Area_Explore", the RTSTAT-6 disappeared and bitstream can be generated successfully after implementation.

Using Synplify and Vivado

Use Synopsys's Synplify to do synthesize and then use Xilinx Vivado to complete implementation. Ref[1] is an article on this.

References
---------------
1. Vivado Implementation 1, http://blog.chinaaet.com/huberyli/p/160952

Difference between Questasim and Modelsim

Used Questasim and Modelsim before. The former is commercial  and the latter is a bit old and can get educational version free. Found the differences of these two tools below from Ref[1].

Questa is Mentor's flagship product that has full System Verilog simulation support. Modelsim is an older product that has limited support for System Verilog. If you plan on using OVM/UVM then you would want to go with Questa, otherwise Modelsim is good enough.

From the following product description pages it looks like Questa's simulation kernel was written to take advantage of multi-core processors, and should have higher performance for large designs. I've never had the opportunity to use Questa for any extended period of time as the places I've worked never wanted to fork over the premium cost over a Modelsim license to get Questa.

Modelsim Product page:
http://www.mentor.com/products/fv/modelsim/

Questa Product page
http://www.mentor.com/products/fv/questa/

Some of the key differences of Questa over ModelSim:
    Compile flow optimizations
    Simulation Performance optimizations (2-50X)
    Post processing analysis (i.e. run a simulation in batch while viewing the results of a previous simulation)
    Multiple Wave Windows
    64-bit mode support (ModelSim is only released to run in 32-bit mode)
    Links to analog/mixed-signal simulation
    Job control and Integration with Simulation farms
    Access to Advanced SystemVerilog Testbench features (assertions, constraints, functional coverage)

References
------------
1. http://www.edaboard.com/thread195003.html

FPGA design step by step using Zed board 1 - A simple project to use SW0 to control LED0

Lets start with a simplest example to use switch 0 to control LED 0 using Zedboard.

1. Create a new project of led_ctrl using vivado.

2. Find the SW0 and LD0 in master xdc file of Zedboard and create a constraint file accordingly below. And add the constraint to the project

# ----------------------------------------------------------------------------
# User LEDs - Bank 33
# ---------------------------------------------------------------------------- 
set_property PACKAGE_PIN T22 [get_ports {LD0}];  # "LD0"


# ----------------------------------------------------------------------------
# User DIP Switches - Bank 35
# ---------------------------------------------------------------------------- 
set_property PACKAGE_PIN F22 [get_ports {SW0}];  # "SW0"

set_property IOSTANDARD LVCMOS33 [get_ports {LD0}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW0}]

The master xdc file for Zedboard can be downloaded at Ref[1]

3. Create a simple verilog file of led_ctrl.v with contents below and added to the project.

`timescale 1ns / 1ps
//led_ctrl.v

module led_ctrl(
       input wire SW0,
       output wire LD0
    );

assign LD0 = SW0;

endmodule

4. Run synthesis and implementation and generate bit file.
5. Download the bitfile to Zedboard.

After that, we can change SW0 positions to turn on and off LED0.

References
--------------
1. master XDC file for Zedboard,  http://zedboard.org/sites/default/files/documentations/zedboard_master_XDC_RevC_D_v3.zip

memory intialization in FPGA

http://www.edaboard.com/thread205601.html
http://myfpgablog.blogspot.com/2011/12/memory-initialization-methods.html

Convert bit file to mcs file for Xilinx FPGA

In vivado, we can convert bit file to mcs file in the tcl console using the write_cfgmem command.

For example, one of the FPGA board that I used has a component of mt28gu01gaax1e-bpi-x16 configuration memory part. In tcl console,

write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 asdf.bit"  asdf.mcs

After that I can program the configuration memory part using the mcs file generated.

The details of the write_cfgmem can be found in Ref[1].

Ref [2] talked about differences between SPI and BPI flash ROM. Here I pasted it below.

SPI protocol is serial type interface. It requires less number of programming pins compare to BPI for configuration. The configuration time is more compare to BPI
- FPGA configures as per industry-standard SPI serial interface protocal
– Mostly used in multi-boot applications where multiple bitstreams can be loaded by the FPGA

BPI protocol is parallel type interface. It requires more number of programming pins compare to SPI for configuration. The configuration time is less compare to SPI
– Uses standard parallel NOR Flash interface
– No clock is needed because the FPGA  contains the control logic
– Flash is easily used as addressable memory with address and data buses. Usually used in embedded applications

References
---------------
1. Vivado Design Suite Tcl Command Reference Guide, UG835(v2014.1) April 2, 2014.
2. SPI vs BPI flash ROM, https://forums.xilinx.com/t5/7-Series-FPGAs/SPI-versus-BPI-Flash-ROM/td-p/500586
3. Vivado Design Suite User Guid, Programming and Debugging, Section Creating a Configuration Memory File

Two-flop synchronizer and non-blocking assignment

Ref [1] mentioned described using two-flop synchronizers to reduce the probability of meta-stability to a great extent and for all practical purposes to zero. I happened to found such an application of two-flop synchronizers in a tutorial of UART receiver for Zedboard. Here I paste the source codes below.

//  Module   : meta_harden.v
`timescale 1ns/1ps


module meta_harden (
  input            clk_dst,      // Destination clock
  input            rst_dst,      // Reset - synchronous to destination clock
  input            signal_src,   // Asynchronous signal to be synchronized
  output reg       signal_dst    // Synchronized signal
);


//***************************************************************************
// Register declarations
//***************************************************************************

  reg           signal_meta;     // After sampling the async signal, this has
                                 // a high probability of being metastable.
                                 // The second sampling (signal_dst) has
                                 // a much lower probability of being
                                 // metastable

//***************************************************************************
// Code
//***************************************************************************

  always @(posedge clk_dst)
  begin
    if (rst_dst)
    begin
      signal_meta <= 1'b0;
      signal_dst  <= 1'b0;
    end
    else // if !rst_dst
    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst
  end // always

endmodule

In the above example, the first flop is to store signal_src to signal_meta and the second flop is to store signal_meta to signal_dst.

In the example, two nonblocking assignments were used  to implement the two-flop synchronizer.

    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst

Ref [2] described differences of blocking and nonblocking assignment in details.

References
 ----------
1, Advanced Chip Design, Practical Examples in Verilog, 5.5.1 Two-flop synchronizers, Author: Kishore Mitra,
2. FPGA Prototyping By Verilog Examples, XILINX SPARTAN-3 Version, 7.1 Blocking versus nonblocking assignment.
 

Connection PS and PL in Zedboard

Reference
------------
1. http://zedboard.org/content/how-access-data-ddr-ps-side-pl-part
2. https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-One-Adam-Taylor-s-MicroZed-Chronicles-Part/ba-p/418935

Boot PL on a Zynq from SPI

Reference
-----------
1. https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/How-can-I-build-a-mcs-file-to-boot-the-PL-on-a-Zynq-from-SPI/td-p/499496

AXI Interface in FPGA

References
--------------
1. AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)

Put ARM CPU to FPGA

References
------------
1. http://electronics.stackexchange.com/questions/37146/how-do-i-design-my-very-own-arm-based-processors
2. Learn How to Build an AHB based ARM SoC (Part 1) HD, https://www.youtube.com/watch?v=gpAk84qAIqA

Verilog Syntax 2 - Timescale

`timescale 1ns/1ps
means whatever times you mensioned in verilog code will be taken in ns.
#22; //22 ns

Resolution of 1ps means
you can have
#0.001; // 0.001 ns / 1ps as smallest representation of the time.
#0.000123; // this means 0 ns

vivado tip - Save and restore captured data in ILA core

Ref [1] provides info on how to  save and restore captured data in ILA core.
To save, use the following command in the tcl console.
write_hw_ila_data my_hw_ila_data_file.zip [upload_hw_ila_data hw_ila_1]
To restore, use the following command.
display_hw_ila_data [read_hw_ila_data my_hw_ila_data_file.zip]
NOTE: When trying the restore operation, I found "open_hw" needs to be executed at least. Otherwise, it will give error.  So the simplest steps to restore the saved data are below.
1. Launch Vivado
2. Type "open_hw" at tcl console or simply click the icon button of "Open Hardware Manager" to open hardware manager.
3. Type the command "display_hw_ila_data [read_hw_ila_data my_hw_ila_data_file.zip]" to restore the captured data.



Reference
-------------
1. Vivado Design Suite User Guide: Programming and Debugging

Eagle learning notes

Here are some extra notes when learning the book of Make Your Own PCBs with EAGLE : From Schematic Designs to Finished Boards. 

*Install Third-party Libraries
In the book, it mentioned installing the Sparkfun library and the Adafruit library. For a project to use the libraries newly installed, we need to right click the directories of the libraries and select the "use all" menu item in the pop up context menu.

* Undo autorouting
Want to undo the work of autorouting and didn't find any button that can do that. Fortunately I found a tip shared in Ref [1]. Just go to the command input box and enter the command "ripup;". It works.

Reference
-----------
1. http://43oh.com/2011/11/tip-eagle-pcb-undo-autorouting-in-one-step/

Verilog Syntax 1 - Port declaration

Verilog 2001 format for port declaration is simpler than Verilog-1995.

module [module_name]
(
[mode] [data_type] [port_namess],
[mode] [data_type] [port_namess],
...
[mode] [data_type] [port_namess]
);

An example is below.

module eq1
(
    input wire i0, i1,
    output wire eq
);

In Verilog-1995,  port names, modes, and data types are declared separately.
For example,

module eq1(i0, i1, eq); 

//declare mode 

input i0, i1;
output eq;
//declare data type
wire i0, i1;
wire eq;

Reference
----------
1. http://www.asic-world.com/verilog/verilog2k1.html

BASYS2 FPGA Programming using Verilog

When creating a new project for BASYS2 using Xilinx WebPackag Project Navigator, there are some  options to be specified correctly.

1. File -> New Project, In "Create New Project" Dialog,  specify "Top Level Source Type" as "HDL".
2. In project settings, specify the following settings.
Family: Spartan3E.
Device: XC3S100E
Package: CP132
Preferred Language: Verilog
Synthesis Tool: XST(VHDL/Verilog)



Reference
-----------
1. How To Program an FPGA With Xilinx ISE Webpack In Verilog or VHDL, https://www.youtube.com/watch?v=eLOLBYxLXcE

Create schematics and turn into PCB

Reference
----------
1. http://www.instructables.com/id/Draw-Electronic-Schematics-with-CadSoft-EAGLE/
2. http://www.instructables.com/id/Turn-your-EAGLE-schematic-into-a-PCB/