Palladium Tips

* To pre-allocate specific domains for a palladium database to run on in a script, we can use xeset command. The following is an example

debug . -session new2
xeset bpValue {0.5 0.6}
host cemulx120
download
...

* Use Verigen to generate gate-level schematics

We can do this via command line or via xeDebug GUI.
a. Use xeDebug GUI
There is a RTL/Gate tab in xeDebug GUI.

In the above, we added the instance of "." and generated verilog file of default.v. The instance of "." represents the root of the design.

b. Directly use command at command line.
verigen USERLIB TEST_WRP -inst . -out default.v -bus

In the above, USERLIB is the library, TEST_WRP is the top level design cell.

* How to debug ribbon cable connection and PIN assignment for palladium database

For example, we know PIN_WE_CE0_CH0 is supposed to connect to the WE pin of Channel 0 CE0 of a NAND daughter card. We can remove NAND from the daughter card to avoid it to drive the signal. Then we can force PIN_WE_CE0_CH0 to low and measure the voltage of the WE input. Then force PIN_WE_CE0_CH0 to high and measure the voltage of the WE input of the daughter card. If the voltage measured matches with the high/low level of the daughter card input, then the PIN assignment/ribbon cable connection for this signal is correct.