BASYS2 FPGA Programming using Verilog

When creating a new project for BASYS2 using Xilinx WebPackag Project Navigator, there are some  options to be specified correctly.

1. File -> New Project, In "Create New Project" Dialog,  specify "Top Level Source Type" as "HDL".
2. In project settings, specify the following settings.
Family: Spartan3E.
Device: XC3S100E
Package: CP132
Preferred Language: Verilog
Synthesis Tool: XST(VHDL/Verilog)



Reference
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1. How To Program an FPGA With Xilinx ISE Webpack In Verilog or VHDL, https://www.youtube.com/watch?v=eLOLBYxLXcE