Verilog Syntax 1 - Port declaration

Verilog 2001 format for port declaration is simpler than Verilog-1995.

module [module_name]
(
[mode] [data_type] [port_namess],
[mode] [data_type] [port_namess],
...
[mode] [data_type] [port_namess]
);

An example is below.

module eq1
(
    input wire i0, i1,
    output wire eq
);

In Verilog-1995,  port names, modes, and data types are declared separately.
For example,

module eq1(i0, i1, eq); 

//declare mode 

input i0, i1;
output eq;
//declare data type
wire i0, i1;
wire eq;

Reference
----------
1. http://www.asic-world.com/verilog/verilog2k1.html