Two-flop synchronizer and non-blocking assignment

Ref [1] mentioned described using two-flop synchronizers to reduce the probability of meta-stability to a great extent and for all practical purposes to zero. I happened to found such an application of two-flop synchronizers in a tutorial of UART receiver for Zedboard. Here I paste the source codes below.

//  Module   : meta_harden.v
`timescale 1ns/1ps


module meta_harden (
  input            clk_dst,      // Destination clock
  input            rst_dst,      // Reset - synchronous to destination clock
  input            signal_src,   // Asynchronous signal to be synchronized
  output reg       signal_dst    // Synchronized signal
);


//***************************************************************************
// Register declarations
//***************************************************************************

  reg           signal_meta;     // After sampling the async signal, this has
                                 // a high probability of being metastable.
                                 // The second sampling (signal_dst) has
                                 // a much lower probability of being
                                 // metastable

//***************************************************************************
// Code
//***************************************************************************

  always @(posedge clk_dst)
  begin
    if (rst_dst)
    begin
      signal_meta <= 1'b0;
      signal_dst  <= 1'b0;
    end
    else // if !rst_dst
    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst
  end // always

endmodule

In the above example, the first flop is to store signal_src to signal_meta and the second flop is to store signal_meta to signal_dst.

In the example, two nonblocking assignments were used  to implement the two-flop synchronizer.

    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst

Ref [2] described differences of blocking and nonblocking assignment in details.

References
 ----------
1, Advanced Chip Design, Practical Examples in Verilog, 5.5.1 Two-flop synchronizers, Author: Kishore Mitra,
2. FPGA Prototyping By Verilog Examples, XILINX SPARTAN-3 Version, 7.1 Blocking versus nonblocking assignment.