Connection PS and PL in Zedboard

Reference
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1. http://zedboard.org/content/how-access-data-ddr-ps-side-pl-part
2. https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-One-Adam-Taylor-s-MicroZed-Chronicles-Part/ba-p/418935

AXI Interface in FPGA

References
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1. AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)