FPGA design step by step using Zed board 1 - A simple project to use SW0 to control LED0

Lets start with a simplest example to use switch 0 to control LED 0 using Zedboard.

1. Create a new project of led_ctrl using vivado.

2. Find the SW0 and LD0 in master xdc file of Zedboard and create a constraint file accordingly below. And add the constraint to the project

# ----------------------------------------------------------------------------
# User LEDs - Bank 33
# ---------------------------------------------------------------------------- 
set_property PACKAGE_PIN T22 [get_ports {LD0}];  # "LD0"


# ----------------------------------------------------------------------------
# User DIP Switches - Bank 35
# ---------------------------------------------------------------------------- 
set_property PACKAGE_PIN F22 [get_ports {SW0}];  # "SW0"

set_property IOSTANDARD LVCMOS33 [get_ports {LD0}]
set_property IOSTANDARD LVCMOS33 [get_ports {SW0}]

The master xdc file for Zedboard can be downloaded at Ref[1]

3. Create a simple verilog file of led_ctrl.v with contents below and added to the project.

`timescale 1ns / 1ps
//led_ctrl.v

module led_ctrl(
       input wire SW0,
       output wire LD0
    );

assign LD0 = SW0;

endmodule

4. Run synthesis and implementation and generate bit file.
5. Download the bitfile to Zedboard.

After that, we can change SW0 positions to turn on and off LED0.

References
--------------
1. master XDC file for Zedboard,  http://zedboard.org/sites/default/files/documentations/zedboard_master_XDC_RevC_D_v3.zip

Two-flop synchronizer and non-blocking assignment

Ref [1] mentioned described using two-flop synchronizers to reduce the probability of meta-stability to a great extent and for all practical purposes to zero. I happened to found such an application of two-flop synchronizers in a tutorial of UART receiver for Zedboard. Here I paste the source codes below.

//  Module   : meta_harden.v
`timescale 1ns/1ps


module meta_harden (
  input            clk_dst,      // Destination clock
  input            rst_dst,      // Reset - synchronous to destination clock
  input            signal_src,   // Asynchronous signal to be synchronized
  output reg       signal_dst    // Synchronized signal
);


//***************************************************************************
// Register declarations
//***************************************************************************

  reg           signal_meta;     // After sampling the async signal, this has
                                 // a high probability of being metastable.
                                 // The second sampling (signal_dst) has
                                 // a much lower probability of being
                                 // metastable

//***************************************************************************
// Code
//***************************************************************************

  always @(posedge clk_dst)
  begin
    if (rst_dst)
    begin
      signal_meta <= 1'b0;
      signal_dst  <= 1'b0;
    end
    else // if !rst_dst
    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst
  end // always

endmodule

In the above example, the first flop is to store signal_src to signal_meta and the second flop is to store signal_meta to signal_dst.

In the example, two nonblocking assignments were used  to implement the two-flop synchronizer.

    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst

Ref [2] described differences of blocking and nonblocking assignment in details.

References
 ----------
1, Advanced Chip Design, Practical Examples in Verilog, 5.5.1 Two-flop synchronizers, Author: Kishore Mitra,
2. FPGA Prototyping By Verilog Examples, XILINX SPARTAN-3 Version, 7.1 Blocking versus nonblocking assignment.
 

Verilog Syntax 2 - Timescale

`timescale 1ns/1ps
means whatever times you mensioned in verilog code will be taken in ns.
#22; //22 ns

Resolution of 1ps means
you can have
#0.001; // 0.001 ns / 1ps as smallest representation of the time.
#0.000123; // this means 0 ns

Verilog Syntax 1 - Port declaration

Verilog 2001 format for port declaration is simpler than Verilog-1995.

module [module_name]
(
[mode] [data_type] [port_namess],
[mode] [data_type] [port_namess],
...
[mode] [data_type] [port_namess]
);

An example is below.

module eq1
(
    input wire i0, i1,
    output wire eq
);

In Verilog-1995,  port names, modes, and data types are declared separately.
For example,

module eq1(i0, i1, eq); 

//declare mode 

input i0, i1;
output eq;
//declare data type
wire i0, i1;
wire eq;

Reference
----------
1. http://www.asic-world.com/verilog/verilog2k1.html

Case Equality and Four States

I noticed a usage of "===" in a book as following, which confused me.
if (expected_data === rddata_tb)
 ...

After some searching,  it is found that Ref[1] give out a good explanation.
Here I simply put the question and answer here in case the link Ref[1] might be  removed in future.

In the answer below, x means unknown state and z means high impedance state.

Question: 

if (dataoutput[7:0] == 8'bx) begin
and
if (dataoutput[7:0] === 8'bx) begin

After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)

Answer:

Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z.

With the "case equality" operator, ===, x's are compared, and the result is 1.

With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators":

For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, then the result shall be a 1-bit unknown value (x).

Reference
==========
1. What is the difference between == and === in Verilog?
http://stackoverflow.com/questions/5927615/what-is-the-difference-between-and-in-verilog, 12/29/2014.