Case Equality and Four States

I noticed a usage of "===" in a book as following, which confused me.
if (expected_data === rddata_tb)
 ...

After some searching,  it is found that Ref[1] give out a good explanation.
Here I simply put the question and answer here in case the link Ref[1] might be  removed in future.

In the answer below, x means unknown state and z means high impedance state.

Question: 

if (dataoutput[7:0] == 8'bx) begin
and
if (dataoutput[7:0] === 8'bx) begin

After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)

Answer:

Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z.

With the "case equality" operator, ===, x's are compared, and the result is 1.

With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators":

For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, then the result shall be a 1-bit unknown value (x).

Reference
==========
1. What is the difference between == and === in Verilog?
http://stackoverflow.com/questions/5927615/what-is-the-difference-between-and-in-verilog, 12/29/2014.