memory intialization in FPGA

http://www.edaboard.com/thread205601.html
http://myfpgablog.blogspot.com/2011/12/memory-initialization-methods.html

Convert bit file to mcs file for Xilinx FPGA

In vivado, we can convert bit file to mcs file in the tcl console using the write_cfgmem command.

For example, one of the FPGA board that I used has a component of mt28gu01gaax1e-bpi-x16 configuration memory part. In tcl console,

write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 asdf.bit"  asdf.mcs

After that I can program the configuration memory part using the mcs file generated.

The details of the write_cfgmem can be found in Ref[1].

Ref [2] talked about differences between SPI and BPI flash ROM. Here I pasted it below.

SPI protocol is serial type interface. It requires less number of programming pins compare to BPI for configuration. The configuration time is more compare to BPI
- FPGA configures as per industry-standard SPI serial interface protocal
– Mostly used in multi-boot applications where multiple bitstreams can be loaded by the FPGA

BPI protocol is parallel type interface. It requires more number of programming pins compare to SPI for configuration. The configuration time is less compare to SPI
– Uses standard parallel NOR Flash interface
– No clock is needed because the FPGA  contains the control logic
– Flash is easily used as addressable memory with address and data buses. Usually used in embedded applications

References
---------------
1. Vivado Design Suite Tcl Command Reference Guide, UG835(v2014.1) April 2, 2014.
2. SPI vs BPI flash ROM, https://forums.xilinx.com/t5/7-Series-FPGAs/SPI-versus-BPI-Flash-ROM/td-p/500586
3. Vivado Design Suite User Guid, Programming and Debugging, Section Creating a Configuration Memory File

Two-flop synchronizer and non-blocking assignment

Ref [1] mentioned described using two-flop synchronizers to reduce the probability of meta-stability to a great extent and for all practical purposes to zero. I happened to found such an application of two-flop synchronizers in a tutorial of UART receiver for Zedboard. Here I paste the source codes below.

//  Module   : meta_harden.v
`timescale 1ns/1ps


module meta_harden (
  input            clk_dst,      // Destination clock
  input            rst_dst,      // Reset - synchronous to destination clock
  input            signal_src,   // Asynchronous signal to be synchronized
  output reg       signal_dst    // Synchronized signal
);


//***************************************************************************
// Register declarations
//***************************************************************************

  reg           signal_meta;     // After sampling the async signal, this has
                                 // a high probability of being metastable.
                                 // The second sampling (signal_dst) has
                                 // a much lower probability of being
                                 // metastable

//***************************************************************************
// Code
//***************************************************************************

  always @(posedge clk_dst)
  begin
    if (rst_dst)
    begin
      signal_meta <= 1'b0;
      signal_dst  <= 1'b0;
    end
    else // if !rst_dst
    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst
  end // always

endmodule

In the above example, the first flop is to store signal_src to signal_meta and the second flop is to store signal_meta to signal_dst.

In the example, two nonblocking assignments were used  to implement the two-flop synchronizer.

    begin
      signal_meta <= signal_src;
      signal_dst  <= signal_meta;
    end // if rst

Ref [2] described differences of blocking and nonblocking assignment in details.

References
 ----------
1, Advanced Chip Design, Practical Examples in Verilog, 5.5.1 Two-flop synchronizers, Author: Kishore Mitra,
2. FPGA Prototyping By Verilog Examples, XILINX SPARTAN-3 Version, 7.1 Blocking versus nonblocking assignment.
 

Connection PS and PL in Zedboard

Reference
------------
1. http://zedboard.org/content/how-access-data-ddr-ps-side-pl-part
2. https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-One-Adam-Taylor-s-MicroZed-Chronicles-Part/ba-p/418935

Boot PL on a Zynq from SPI

Reference
-----------
1. https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/How-can-I-build-a-mcs-file-to-boot-the-PL-on-a-Zynq-from-SPI/td-p/499496

AXI Interface in FPGA

References
--------------
1. AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)

Put ARM CPU to FPGA

References
------------
1. http://electronics.stackexchange.com/questions/37146/how-do-i-design-my-very-own-arm-based-processors
2. Learn How to Build an AHB based ARM SoC (Part 1) HD, https://www.youtube.com/watch?v=gpAk84qAIqA